1. Field of the Invention
The present invention relates to an interrupt signal processing apparatus connected between two processing devices each operating on an operation clock having a different clock speed, which is adapted to perform processing in response to an interrupt request signal.
2. Description of the Related Art
An information processing device such as a personal computer generally uses a plurality of arithmetic computing devices which operates on operation clocks each having a different clock speed in order to improve its performance and to reduce power consumption. Such arithmetic computing devices include, for example, a main arithmetic computing device called a main processor used to entirely control information processing auxiliary arithmetic computing device called an auxiliary processor used to exclusively perform, for example, image processing.
There are some cases in which the main and auxiliary arithmetic computing devices make a request for interruptions to each other, when a signal requesting the interrupt processing is output from one arithmetic computing device to the other arithmetic computing device. As described above, since the one processing device and the other processing device operate on operation clocks each having a different clock speed, each of the processing devices has to perform interrupt processing in synchronization with these operation clocks.
In a conventional interrupt signal processing apparatus, for example, when the main processor operating on a high-speed clock generates an interruption to the auxiliary processor, to notify the generation of the interruption, an interrupt setting pulse signal using timing provided by the high speed clock on which the main processor operates is produced and set to a register. The interrupt signal processing apparatus outputs, based on the interrupt setting pulse signal set to the register, an interruption requesting signal using timing provided by the low speed clock on which the auxiliary processor operates, to the auxiliary processor. This causes the auxiliary processor to recognize the request for interruptions from the main processor.
Moreover, the interrupt signal processing apparatus, when receiving an interrupt clearing pulse signal notifying that the auxiliary processor has terminated the interruption processing in response to the interruption request from the auxiliary processor, produces an interrupt clearing pulse signal using the timing provided by the low speed clock on which the auxiliary processor operates and outputs it to the register in order to clear the register.
The interrupt signal processing apparatus, when the register is cleared, outputs an interrupt permission signal using the timing provided by the high speed clock to the main processor. This causes the main processor to recognize that a new interruption can be generated and to generate the new interruption if necessary.
By the interrupt signal processing apparatus, an interruption is generated from the one processing device operating on a high-speed clock to the other processing device operating on a low-speed clock.
In the interrupt signal processing apparatus, due to outputting of the interrupt permission signal, the interrupt clearing request signal is input from the processing device operating on the low speed clock, however, if the interrupt setting pulse from the processing device operating on the high speed clock is input while the interrupt clearing request signal is being input, a malfunction occurs due to the duplicate inputting of signals to the register in the interrupt signal processing apparatus. To avoid this malfunction, an interrupt setting priority function is provided which, by using an interrupt setting pulse signal being operated to control so as to stop outputting of the interrupt clearing pulse signal to the register using the timing provided by the high speed clock, controls the interrupt clearing pulse signal.
However, such the conventional interrupt signal processing apparatus has a problem. That is, since there is a difference in the clock speed between the two processing devices, the pulse signal to respond to the one processing device operating on the low-speed operation clock has to be controlled by the pulse signal to respond to the other processing device operating on the high-speed operation clock. Because of this, an interrupt signal processing device having the interrupt clearing priority function, which is the reverse of the interrupt setting priority function, is required to respond to a request for the interruption from the processing device operating on the low speed clock to the processing device operating on the high speed clock. Therefore, when the interruption between both the processing devices is to be generated by using the conventional interrupt signal processing apparatus, it is necessary to switch between the interrupt priority function and the interrupt clearing priority function by taking a relation in speeds of operation clocks into consideration.
In view of the above, it is an object of the present invention to provide an interrupt signal processing apparatus capable of implementing an interruption without considerations given to a difference in a clock speed between two processing devices. It is another object of the present invention to provide the interrupt signal processing apparatus capable of implementing the interruption without the need for a priority function switching mechanism and without the need for switching operations.
According to a first aspect of the present invention, there is provided an interrupt signal processing apparatus for processing a request for interruption from one device to the other device, connected between the one device and the other device, each being operated on either of a first clock and a second clock, including:
an interrupt setting pulse generating section, when receiving an interrupt requesting signal from the one device, generates an interrupt setting pulse signal by using timing provided by the first clock on which the one device is operated;
a register, when receiving the interrupt setting pulse signal, to store the interrupt setting pulse signal as a signal for interruption to the other device;
a first synchronization unit to output the interrupt signal fed from the register to the other device, in synchronization with the second clock on which the other device is operated;
an interrupt clearing pulse generating section, when receiving an interrupt clearing request signal from the other device which has received the interrupt signal through the synchronization section, to output an interrupt clearing pulse signal using timing provided by the second clock in order to reset the register used to store the interrupt signal;
a second synchronization section to output an interrupt permission signal, in synchronization with the first clock, to the one device, when the register has received the clearing pulse signal;
a control circuit provided between the interrupt setting pulse generating section and the interrupt clearing pulse generating section to control generation, using one pulse out of the interrupt setting pulse signal and the interrupt clearing pulse signal, of the other pulse out of the interrupt setting pulse and the interrupt clearing signal; and
a delay circuit to provide, while the one pulse signal is being input to the register, a time delay to operations of the synchronization section being operated in synchronization with the clock on which the pulse generating section used to generate the other pulse signal is operated, in order to prevent duplicated inputting of the both pulse signals to the register.
In the foregoing, a preferable mode is one wherein each of the first and second clocks has a different clock speed.
Also, a preferable mode is one wherein a speed of the clock on which the pulse generating section to generate the one of the pulse signals is operated is lower than that of the clock on which the pulse generating section to generate the other of the pulse signals is operated and wherein the delay circuit provides a time delay being equivalent to a clock period of the low-speed clock to the synchronization section.
Also, a preferable mode is one wherein the register is made up of a flip-flop having a set terminal, a reset terminal and an output terminal in which an output signal is switched between two values by selective inputting of a signal to both terminals and wherein the interrupt setting pulse signal is input to the set terminal and the interrupt clearing pulse is input to the reset terminal and wherein an output signal from the output terminal is input to the both synchronization sections.
Also, a preferable mode is one wherein the control circuit, while the interrupt setting pulse signal is being input in the register, controls the interrupt clearing pulse generating section in order to stop generation of the interrupt clearing pulse generating section by the interrupt clearing pulse generating section and wherein the delay circuit, while the interrupt setting pulse signal is outputting from the interrupt setting pulse generating section, provides a time delay to the transmission of the interrupt signal fed from the register to the first synchronization section.
Also, a preferable mode is one wherein the control circuit, while the interrupt clearing pulse signal is being input to the register, controls the interrupt setting pulse generating section in order to stop the generation of the interrupt setting pulse signal and wherein the control circuit, while the interrupt clearing pulse signal is outputting from the interrupt clearing pulse generating section, provides a time delay to the transmission of an interrupt permission signal fed from the register to the second synchronization section.
Also, a preferable mode is one wherein the delay circuit is made up of a D flip-flop having a clock input terminal, data input terminal and output terminal and wherein the first clock is input to the clock input terminal and the interrupt permission signal fed from the register to the second synchronization section is input and the interrupt permission signal is output to the output terminal in synchronization with operations of the clock terminal.
Also, a preferable mode is one wherein the delay circuit is made up of a D flip-flop having a clock input terminal to which the second clock is input, a data input terminal to which the interrupt signal fed from the register to the first synchronization section is input and an output terminal which outputs the interrupt signal in synchronization with operations of the clock terminal and is made up of an OR circuit to which the interrupt signal fed from the output terminal of the D flip-flop and the interrupt permission signal fed from the register are input and wherein an output from the OR circuit is input to the first synchronization section.
Also, a preferable mode is one wherein the delay circuit is made up of an AND circuit to which an output signal fed from the register and a reversed signal of the interrupt setting pulse are input and wherein an output of the logical circuit is input to the both synchronization sections.
Also, a preferable mode is one wherein the delay circuit is made up of an OR circuit to which an output signal fed from the register and the interrupt clearing pulse are input and wherein an output from the OR circuit is input to the both synchronization sections.
Also, a preferable mode is one wherein the interrupt setting pulse generating section is made up of a D first flip-flop having a data input terminal to which the interrupt requesting signal fed from the one device is input, a clock input terminal to which the first clock is input and an output terminal from which the signal is output with a delay being equivalent to one clock period of the first clock in synchronization with the first clock and of a second D flip-flop having a data input terminal to which the signal is input from the output terminal, a clock input terminal to which the first clock is input and an output terminal from which a reversed signal of the signal with a delay being equivalent to one clock period of the first clock is output in synchronization with the clock terminal and of an OR circuit to which the both signals fed from the output terminals of the first and second D flip-flop are input and wherein the AND circuit outputs, in synchronization with the first clock, one pulse with a pulse width being equivalent to one clock period of the first clock, as the interrupt setting pulse signal to the register.
Also, a preferable mode is one wherein the second D flip-flop has a set input terminal receiving a control signal from the control circuit and outputs, while receiving the control signal, the reversed signal to the output terminal, which causes the interrupt setting pulse generating section, while receiving the control signal from the control circuit, to stop the outputting of the interrupt setting pulse signal.
Also, a preferable mode is one wherein the interrupt clearing pulse generating section is made up of a first D flip-flop having a data input terminal to which the interrupt clearing request signal fed from the other device is input, a clock input terminal to which the second clock is input and an output terminal which outputs the signal with a delay being equivalent to one clock period of the second clock in synchronization with the second clock and of a second D flip-flop having a data input terminal to which the signal fed from the output terminal is input, a clock input terminal to which the second clock is input and an output terminal which outputs a reversed signal of the signal with a delay being equivalent to one clock period of the clock in synchronization with operations of the clock terminal and of an AND circuit to which the both signals fed from the output terminals of the first and second D flip-flop are input, wherein the AND circuit outputs one pulse having a pulse width being equivalent to one clock period of the second clock as the interrupt clearing pulse signal, in synchronization with the second clock, to the register.
Also, a preferable mode is one wherein the second D flip-flop has a set input terminal receiving a control signal from the control circuit and outputs, while receiving the control signal, the reversed signal to the output terminal, which causes the interrupt clearing pulse generating section, while receiving the control signal from the control circuit, to stop the outputting of the interrupt clearing pulse signal.
Also, a preferable mode is one wherein the first synchronization section is provided with a first D flip-flop having a data input terminal to which the interrupt signal is input from the delay circuit, a clock input terminal to which the second clock is input and an output terminal which outputs the signal with a delay being equivalent to one clock period of the second clock in synchronization with the clock and with a second D flip-flop having a data input terminal to which the signal is input from the output terminal, a clock input terminal to which the clock is input and an output terminal which outputs the signal with a delay being equivalent to one clock period of the second clock in synchronization with the second clock, to the other device.
Also, a preferable mode is one wherein the second synchronization section is made up of a first D flip-flop having a data input terminal to which the interrupt permission signal is input from the delay circuit, a clock input terminal to which the first clock is input and an output terminal which outputs the signal with a delay being equivalent to one clock period of the first clock in synchronization with the first clock and of a second D flip-flop having a data input terminal to which the signal is input from the output terminal, a clock input terminal to which the first clock is input and an output terminal which outputs the signal with a delay being equivalent to one clock period of the first clock in synchronization with the first clock, to the one device.